74HC00PW,112

Identity

• Manufacturer: Nexperia(安世)
• Model / MPN: 74HC00PW,112
• LCSC: C546477
• Category: logic-gate
• Description: 74HC00PW,112 2V6V Logic Type:NAND Gate Number of Channels:4 Voltage - Supply:2V6V Voltage - Supply:2V~6V Quiescent Current:40uA Current - Output Low(IOL):5.2mA Current - Output High(IOH):5.2mA Input Logic Level - High:1.5V；4.2V；3.15V Input Logic Level - High:1.5V；4.2V；3.1
• Source: EasyEDA/JLC verified common component seed
• Project designators: Not project-specific
• Project quantity per board: Not project-specific

Capabilities

• gpio: interface

Package And Footprint

• Package / footprint name: TSSOP-14
• Pin count: 14
• EasyEDA symbol UUID: 8723cc00449e4534add777f98baac074
• EasyEDA footprint UUID: 16caf36bcd4b4669aecfeec7af193aad
• EasyEDA device UUID: 2603b2c8c91f42439de6544f11c1da61
• EasyEDA library UUID: 0819f05c4eef4c71ace90d822a990e87

Power And Operating Modes

• Active current: Not characterized in seed; extract active current from datasheet tables.
• Sleep / standby current: Not characterized in seed; extract sleep/standby current from datasheet tables.
• Supply rails: EasyEDA property: 2V~6V.
• Notes: Seed values are search hints only. Verify power modes, rail limits, startup requirements, and reference design passives from the datasheet.

Procurement Classification

• JLC class: Extended Part
• JLC note / assembly basis: EasyEDA/JLC verified common logic, level-shifting, bus-interface, and analog-switch seed
• Assembly status: jlc_extended
• Price-break table: Not captured in seed. Store only timestamped price-break snapshots when intentionally refreshed.
• Live stock: intentionally not stored as durable selection data; refresh externally before ordering.

Datasheet And Links

• Datasheet / product URL: https://item.szlcsc.com/datasheet/74HC00PW%252C112/567607.html
• Product URL: https://item.szlcsc.com/datasheet/74HC00PW%252C112/567607.html
• Datasheet-derived notes: Not extracted yet. Use PDF extraction to fill power modes, absolute maximums, pin functions, package variants, and reference design requirements.

Selection Notes

• Good for: small glue logic, signal qualification, enable gating, reset/boot strap logic, and simple digital interlocks
• Avoid when: Not captured yet.
• Known layout constraints: Verify package land pattern, decoupling requirements, thermal pad, RF keepouts, crystal routing, and boot straps from the datasheet.
• Equivalent search hints: match category logic-gate, interfaces gpio, package TSSOP-14, and EasyEDA footprint UUID 16caf36bcd4b4669aecfeec7af193aad.

Search Keywords

seed:common-logic-interface-glue, source:easyeda-bridge, iot, common-pcb, logic, interface, glue, 74hc00, quad-nand, tssop, logic-gate, tssop-14, jlc-extended, gpio, jlc_extended, jlc-note:easyeda-jlc-verified-common-logic-level-shifting-bus-interface-and-analog-switch-seed