TXS0102VDCTR

Identity

• Manufacturer: TI(德州仪器)
• Model / MPN: TXS0102VDCTR
• LCSC: C42138858
• Category: level-shifter
• Description: 2-bit bidirectional level shifter for open-drain and push-pull; 24Mbps; 2Mbps; VCCA 1.65V3.6V, VCCB 2.3V5.5V; 2 circuits
• Source: EasyEDA/JLC verified common component seed
• Project designators: Not project-specific
• Project quantity per board: Not project-specific

Capabilities

• gpio: interface

Package And Footprint

• Package / footprint name: SSOP-8
• Pin count: 8
• EasyEDA symbol UUID: 7f658b64e24248d7824d6b3df08edee4
• EasyEDA footprint UUID: 41952e874d654784a02eee873b3560f1
• EasyEDA device UUID: f5d0195f81c647febafa45528ea85076
• EasyEDA library UUID: 0819f05c4eef4c71ace90d822a990e87

Power And Operating Modes

• Active current: Not characterized in seed; extract active current from datasheet tables.
• Sleep / standby current: Not characterized in seed; extract sleep/standby current from datasheet tables.
• Supply rails: Not characterized in seed; capture allowed supply rail range from datasheet.
• Notes: Seed values are search hints only. Verify power modes, rail limits, startup requirements, and reference design passives from the datasheet.

Procurement Classification

• JLC class: Extended Part
• JLC note / assembly basis: EasyEDA/JLC verified common logic, level-shifting, bus-interface, and analog-switch seed
• Assembly status: jlc_extended
• Price-break table: Not captured in seed. Store only timestamped price-break snapshots when intentionally refreshed.
• Live stock: intentionally not stored as durable selection data; refresh externally before ordering.

Datasheet And Links

• Datasheet / product URL: https://www.ti.com/cn/lit/ds/symlink/txs0102v.pdf
• Product URL: https://www.ti.com/cn/lit/ds/symlink/txs0102v.pdf
• Datasheet-derived notes: Not extracted yet. Use PDF extraction to fill power modes, absolute maximums, pin functions, package variants, and reference design requirements.

Selection Notes

• Good for: reuse when package, electrical ratings, footprint, and assembly class match the project constraints
• Avoid when: Not captured yet.
• Known layout constraints: Verify package land pattern, decoupling requirements, thermal pad, RF keepouts, crystal routing, and boot straps from the datasheet.
• Equivalent search hints: match category level-shifter, interfaces gpio, package SSOP-8, and EasyEDA footprint UUID 41952e874d654784a02eee873b3560f1.

Search Keywords

seed:common-logic-interface-glue, source:easyeda-bridge, iot, common-pcb, logic, interface, glue, txs0102, 2-bit, auto-direction, bidirectional, voltage-translation, level-shifter, ssop-8, jlc-extended, gpio, jlc_extended, jlc-note:easyeda-jlc-verified-common-logic-level-shifting-bus-interface-and-analog-switch-seed