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CD4053

C2943322

Triple 2-channel analog multiplexer/demultiplexer, -6V~0V/3V~9V, Switch Circuit:2:1, 3 channels, Ron:350Ω, 40MHz, tpd:10ns, -40°C~+85°C

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Datasheet or product page datasheet
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Datasheet PDF (mirrored) datasheet pdf
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DIP-16 easyeda footprint
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EasyEDA Pro device: C2943322 easyeda pro device
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EasyEDA Pro library (device+symbol+footprint): C2943322 easyeda pro lib
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JLC/LCSC product image jlc image
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engineering profile

CD4053

Identity

  • Manufacturer: I-CORE(中微爱芯)
  • Model / MPN: CD4053
  • LCSC: C2943322
  • Category: analog-switch
  • Description: Triple 2-channel analog multiplexer/demultiplexer, -6V0V/3V9V, Switch Circuit:2:1, 3 channels, Ron:350Ω, 40MHz, tpd:10ns, -40°C~+85°C
  • Source: EasyEDA/JLC verified common component seed
  • Project designators: Not project-specific
  • Project quantity per board: Not project-specific

Capabilities

  • analog: interface
  • gpio: interface

Package And Footprint

  • Package / footprint name: DIP-16
  • Pin count: Unknown
  • EasyEDA symbol UUID: b2604219f22c4d3f8ee93a4eaedcdeea
  • EasyEDA footprint UUID: 387429edf99c4b1691a005079f1d8f23
  • EasyEDA device UUID: e700fc7af33e44f288bc0f79b74fb287
  • EasyEDA library UUID: 0819f05c4eef4c71ace90d822a990e87

Power And Operating Modes

  • Active current: Passive part; no quiescent current.
  • Sleep / standby current: Passive part; no quiescent current.
  • Supply rails: Application-defined.
  • Notes: Ratings are seeded from EasyEDA/LCSC properties when present; verify against datasheet for final design.

Procurement Classification

  • JLC class: Extended Part
  • JLC note / assembly basis: EasyEDA/JLC verified common logic, level-shifting, bus-interface, and analog-switch seed
  • Assembly status: jlc_extended
  • Price-break table: Not captured in seed. Store only timestamped price-break snapshots when intentionally refreshed.
  • Live stock: intentionally not stored as durable selection data; refresh externally before ordering.

Datasheet And Links

Selection Notes

  • Good for: routing analog sensor paths, audio/control signals, low-resistance SPST/SPDT switching, and selectable measurement paths
  • Avoid when: Not captured yet.
  • Known layout constraints: Verify package land pattern, decoupling requirements, thermal pad, RF keepouts, crystal routing, and boot straps from the datasheet.
  • Equivalent search hints: match category analog-switch, interfaces analog, gpio, package DIP-16, and EasyEDA footprint UUID 387429edf99c4b1691a005079f1d8f23.

Search Keywords

seed:common-logic-interface-glue, source:easyeda-bridge, iot, common-pcb, logic, interface, glue, cd4053, triple-spdt, analog-switch, mux, routing, dip-16, jlc-extended, analog, gpio, jlc_extended, jlc-note:easyeda-jlc-verified-common-logic-level-shifting-bus-interface-and-analog-switch-seed

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