CD4051
Identity
- Manufacturer: I-CORE(中微爱芯)
- Model / MPN: CD4051
- LCSC: C2943321
- Category: analog-mux
- Description: 8:1 analog switch, 3V
9V, 8 channels, Ron:115Ω, on 280ns, Bandwidth:40MHz/13MHz, tpd:15ns, -40°C+85°C - Source: EasyEDA/JLC verified common component seed
- Project designators: Not project-specific
- Project quantity per board: Not project-specific
Capabilities
- analog: interface
- gpio: interface
Package And Footprint
- Package / footprint name: TSSOP-16
- Pin count: 16
- EasyEDA symbol UUID: 522f86c961a348ce8332d179d4706306
- EasyEDA footprint UUID: a11950ceac50438289ff689a35fd9574
- EasyEDA device UUID: 9142c473279447d19e9bc390406745ef
- EasyEDA library UUID: 0819f05c4eef4c71ace90d822a990e87
Power And Operating Modes
- Active current: Not characterized in seed; extract active current from datasheet tables.
- Sleep / standby current: Not characterized in seed; extract sleep/standby current from datasheet tables.
- Supply rails: EasyEDA property: 3V~9V.
- Notes: Seed values are search hints only. Verify power modes, rail limits, startup requirements, and reference design passives from the datasheet.
Procurement Classification
- JLC class: Extended Part
- JLC note / assembly basis: EasyEDA/JLC verified common logic, level-shifting, bus-interface, and analog-switch seed
- Assembly status: jlc_extended
- Price-break table: Not captured in seed. Store only timestamped price-break snapshots when intentionally refreshed.
- Live stock: intentionally not stored as durable selection data; refresh externally before ordering.
Datasheet And Links
- Datasheet / product URL: https://item.szlcsc.com/datasheet/CD4051/3325980.html
- Product URL: https://item.szlcsc.com/datasheet/CD4051/3325980.html
- Datasheet-derived notes: Not extracted yet. Use PDF extraction to fill power modes, absolute maximums, pin functions, package variants, and reference design requirements.
Selection Notes
- Good for: multiplexing analog sensors, ADC inputs, resistor ladders, and configurable measurement paths
- Avoid when: Not captured yet.
- Known layout constraints: Verify package land pattern, decoupling requirements, thermal pad, RF keepouts, crystal routing, and boot straps from the datasheet.
- Equivalent search hints: match category
analog-mux, interfaces analog, gpio, packageTSSOP-16, and EasyEDA footprint UUIDa11950ceac50438289ff689a35fd9574.
Search Keywords
seed:common-logic-interface-glue, source:easyeda-bridge, iot, common-pcb, logic, interface, glue, cd4051, 8-channel, analog-multiplexer, sensor-mux, tssop, analog-mux, tssop-16, jlc-extended, analog, gpio, jlc_extended, jlc-note:easyeda-jlc-verified-common-logic-level-shifting-bus-interface-and-analog-switch-seed