GD25Q16CTEGR

Identity

• Manufacturer: GigaDevice(兆易创新)
• Model / MPN: GD25Q16CTEGR
• LCSC: C2915647
• Category: flash-memory
• Description: GD25Q16CTEGR 2.7V3.6V SPI Interface:SPI Memory Size:16Mbit Clock Frequency:120MHz Voltage - Supply:2.7V3.6V Voltage - Supply:2.7V~3.6V Standby Supply Current:1uA Program / Erase Cycles:100,000 Cycles Page Programming Time (Tpp):600us Block Erase Time(tBE):- Data Retention - TDR (
• Source: EasyEDA/JLC verified common component seed
• Project designators: Not project-specific
• Project quantity per board: Not project-specific

Capabilities

• spi: interface

Package And Footprint

• Package / footprint name: SOP-8
• Pin count: 8
• EasyEDA symbol UUID: db24fc1eca4a4ea294d6ab7526e30424
• EasyEDA footprint UUID: 114ea734da1646a1859a103ac7dff343
• EasyEDA device UUID: 62c53b077d3a42f9a302ecb74b2f1e45
• EasyEDA library UUID: 0819f05c4eef4c71ace90d822a990e87

Power And Operating Modes

• Active current: Not characterized in seed; extract active current from datasheet tables.
• Sleep / standby current: Not characterized in seed; extract sleep/standby current from datasheet tables.
• Supply rails: EasyEDA property: 2.7V~3.6V.
• Notes: Seed values are search hints only. Verify power modes, rail limits, startup requirements, and reference design passives from the datasheet.

Procurement Classification

• JLC class: Extended Part
• JLC note / assembly basis: EasyEDA/JLC verified common memory, timing, storage, and security seed
• Assembly status: jlc_extended
• Price-break table: Not captured in seed. Store only timestamped price-break snapshots when intentionally refreshed.
• Live stock: intentionally not stored as durable selection data; refresh externally before ordering.

Datasheet And Links

• Datasheet / product URL: https://item.szlcsc.com/datasheet/GD25Q16CTEGR/3209581.html
• Product URL: https://item.szlcsc.com/datasheet/GD25Q16CTEGR/3209581.html
• Datasheet-derived notes: Not extracted yet. Use PDF extraction to fill power modes, absolute maximums, pin functions, package variants, and reference design requirements.

Selection Notes

• Good for: external firmware storage, OTA staging, logs, filesystems, fonts, assets, and calibration blobs over SPI/QSPI
• Avoid when: Not captured yet.
• Known layout constraints: Verify package land pattern, decoupling requirements, thermal pad, RF keepouts, crystal routing, and boot straps from the datasheet.
• Equivalent search hints: match category flash-memory, interfaces spi, package SOP-8, and EasyEDA footprint UUID 114ea734da1646a1859a103ac7dff343.

Search Keywords

seed:common-memory-timing-security, source:easyeda-bridge, iot, common-pcb, storage, timing, security, gd25q16, spi-nor, 16mbit, gigadevice, sop-8, flash-memory, jlc-extended, spi, jlc_extended, jlc-note:easyeda-jlc-verified-common-memory-timing-storage-and-security-seed