HT7333-A-EV
Identity
- Manufacturer: Unknown
- Model / MPN: HT7333-A-EV
- LCSC: C28642151
- Category: ldo-regulator
- Description: HT7333-A-EV Output Type:Fixed Maximum Input Voltage:24V Output Voltage:3.3V Output Voltage:3.3V Output Current:300mA Output Polarity:Positive electrode
- Source: EasyEDA/JLC verified common component seed
- Project designators: Not project-specific
- Project quantity per board: Not project-specific
Capabilities
- Not captured yet.
Package And Footprint
- Package / footprint name: SOT-89
- Pin count: Unknown
- EasyEDA symbol UUID: a4abe65f794e4837843d39976c280d3a
- EasyEDA footprint UUID: b9cd25d9321542ccbea9addb38d12d8e
- EasyEDA device UUID: 0cdb949ae684451cbd20c6766b642168
- EasyEDA library UUID: 0819f05c4eef4c71ace90d822a990e87
Power And Operating Modes
- Active current: Not characterized in seed; extract active current from datasheet tables.
- Sleep / standby current: Not characterized in seed; extract sleep/standby current from datasheet tables.
- Supply rails: Not characterized in seed; capture allowed supply rail range from datasheet.
- Notes: Seed values are search hints only. Verify power modes, rail limits, startup requirements, and reference design passives from the datasheet.
Procurement Classification
- JLC class: Extended Part
- JLC note / assembly basis: EasyEDA/JLC verified common power, analog, and interface IC seed
- Assembly status: jlc_extended
- Price-break table: Not captured in seed. Store only timestamped price-break snapshots when intentionally refreshed.
- Live stock: intentionally not stored as durable selection data; refresh externally before ordering.
Datasheet And Links
- Datasheet / product URL: https://item.szlcsc.com/datasheet/HT7333-A-EV/30380337.html
- Product URL: https://item.szlcsc.com/datasheet/HT7333-A-EV/30380337.html
- Datasheet-derived notes: Not extracted yet. Use PDF extraction to fill power modes, absolute maximums, pin functions, package variants, and reference design requirements.
Selection Notes
- Good for: power-tree designs when ratings and layout constraints fit
- Avoid when: Not captured yet.
- Known layout constraints: Verify package land pattern, decoupling requirements, thermal pad, RF keepouts, crystal routing, and boot straps from the datasheet.
- Equivalent search hints: match category
ldo-regulator, interfaces none captured, packageSOT-89, and EasyEDA footprint UUIDb9cd25d9321542ccbea9addb38d12d8e.
Search Keywords
seed:common-power-analog-interface, source:easyeda-bridge, iot, common-pcb, ht7333, 3.3v, high-input-voltage, sot-89, ldo-regulator, jlc-extended, jlc_extended, jlc-note:easyeda-jlc-verified-common-power-analog-and-interface-ic-seed