SN74LV1T34DBVRG4

Identity

Manufacturer: TI(德州仪器)
Model / MPN: SN74LV1T34DBVRG4
LCSC: C1848228
Category: logic-buffer
Description: SN74LV1T34DBVRG4 1.6V~~5.5V Input type:- output type:Push-pull Voltage - Supply:1.6V~~5.5V Voltage - Supply:1.6V~5.5V Number of Elements:1 Number of Bits per Element:1 Channel Type:- Current - Output Low(IOL):8mA Current - Output High(IOH):8mA Logic Family:74LV1T Operating Temperatur
Source: EasyEDA/JLC verified common component seed
Project designators: Not project-specific
Project quantity per board: Not project-specific

Capabilities

gpio: interface

Package And Footprint

Package / footprint name: SOT-23-5
Pin count: 5
EasyEDA symbol UUID: 3f8003ac6478427f9e670813016bd40b
EasyEDA footprint UUID: 3962fa5424e54dde8cfd30751ab1c7e4
EasyEDA device UUID: 611b7c28fe0a4bd1a949c71a690652e9
EasyEDA library UUID: 0819f05c4eef4c71ace90d822a990e87

Power And Operating Modes

Active current: Not characterized in seed; extract active current from datasheet tables.
Sleep / standby current: Not characterized in seed; extract sleep/standby current from datasheet tables.
Supply rails: EasyEDA property: 1.6V~5.5V.
Notes: Seed values are search hints only. Verify power modes, rail limits, startup requirements, and reference design passives from the datasheet.

Procurement Classification

JLC class: Extended Part
JLC note / assembly basis: EasyEDA/JLC verified common logic, level-shifting, bus-interface, and analog-switch seed
Assembly status: jlc_extended
Price-break table: Not captured in seed. Store only timestamped price-break snapshots when intentionally refreshed.
Live stock: intentionally not stored as durable selection data; refresh externally before ordering.

Datasheet And Links

Datasheet / product URL: https://www.ti.com/cn/lit/gpn/sn74lv1t34
Product URL: https://www.ti.com/cn/lit/gpn/sn74lv1t34
Datasheet-derived notes: Not extracted yet. Use PDF extraction to fill power modes, absolute maximums, pin functions, package variants, and reference design requirements.

Selection Notes

Good for: single-signal buffering, edge cleanup, simple fanout, and fixed-direction logic-level interfaces
Avoid when: Not captured yet.
Known layout constraints: Verify package land pattern, decoupling requirements, thermal pad, RF keepouts, crystal routing, and boot straps from the datasheet.
Equivalent search hints: match category logic-buffer, interfaces gpio, package SOT-23-5, and EasyEDA footprint UUID 3962fa5424e54dde8cfd30751ab1c7e4.

Search Keywords

seed:common-logic-interface-glue, source:easyeda-bridge, iot, common-pcb, logic, interface, glue, sn74lv1t34, single-buffer, logic-level, fixed-direction, sot-23, logic-buffer, sot-23-5, jlc-extended, gpio, jlc_extended, jlc-note:easyeda-jlc-verified-common-logic-level-shifting-bus-interface-and-analog-switch-seed