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74HC4052

C111594

Dual 4:1 analog switch, 3V~9V, Switch Circuit:4:1, 2 channels, Ron:115Ω, Bandwidth:40MHz, tpd:10ns, -40°C~+85°C

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Datasheet or product page datasheet
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Datasheet PDF (mirrored) datasheet pdf
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SOP-16 easyeda footprint
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EasyEDA Pro device: C111594 easyeda pro device
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JLC/LCSC product image jlc image
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engineering profile

74HC4052

Identity

  • Manufacturer: I-CORE(中微爱芯)
  • Model / MPN: 74HC4052
  • LCSC: C111594
  • Category: analog-mux
  • Description: Dual 4:1 analog switch, 3V9V, Switch Circuit:4:1, 2 channels, Ron:115Ω, Bandwidth:40MHz, tpd:10ns, -40°C+85°C
  • Source: EasyEDA/JLC verified common component seed
  • Project designators: Not project-specific
  • Project quantity per board: Not project-specific

Capabilities

  • analog: interface
  • gpio: interface

Package And Footprint

  • Package / footprint name: SOP-16
  • Pin count: 16
  • EasyEDA symbol UUID: fb996c4f0b074c97933287a0d42c5c8b
  • EasyEDA footprint UUID: e52e644bbb3548988fcc9af5d7d48159
  • EasyEDA device UUID: a96ff5f8487d4cb4be61f979a9ec7ff3
  • EasyEDA library UUID: 0819f05c4eef4c71ace90d822a990e87

Power And Operating Modes

  • Active current: Not characterized in seed; extract active current from datasheet tables.
  • Sleep / standby current: Not characterized in seed; extract sleep/standby current from datasheet tables.
  • Supply rails: EasyEDA property: 3V~9V.
  • Notes: Seed values are search hints only. Verify power modes, rail limits, startup requirements, and reference design passives from the datasheet.

Procurement Classification

  • JLC class: Extended Part
  • JLC note / assembly basis: EasyEDA/JLC verified common logic, level-shifting, bus-interface, and analog-switch seed
  • Assembly status: jlc_extended
  • Price-break table: Not captured in seed. Store only timestamped price-break snapshots when intentionally refreshed.
  • Live stock: intentionally not stored as durable selection data; refresh externally before ordering.

Datasheet And Links

Selection Notes

  • Good for: multiplexing analog sensors, ADC inputs, resistor ladders, and configurable measurement paths
  • Avoid when: Not captured yet.
  • Known layout constraints: Verify package land pattern, decoupling requirements, thermal pad, RF keepouts, crystal routing, and boot straps from the datasheet.
  • Equivalent search hints: match category analog-mux, interfaces analog, gpio, package SOP-16, and EasyEDA footprint UUID e52e644bbb3548988fcc9af5d7d48159.

Search Keywords

seed:common-logic-interface-glue, source:easyeda-bridge, iot, common-pcb, logic, interface, glue, 74hc4052, dual-4-channel, analog-multiplexer, sensor-mux, analog-mux, sop-16, jlc-extended, analog, gpio, jlc_extended, jlc-note:easyeda-jlc-verified-common-logic-level-shifting-bus-interface-and-analog-switch-seed

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